[hcs-d] TALK: Enabling CPU/GPU Portability via Execution Model Translation Speaker (Gregory Diamos from Georgia Tech, Thursday April 14th, 7:35 PM, Harvard Hall 104)

Nicolas Pinto pinto at mit.edu
Tue Apr 12 18:39:01 EDT 2011

Title: Enabling CPU/GPU Portability via Execution Model Translation
Speaker: Gregory Diamos (Georgia Tech)

Date: 4-14-2011
Time: 7:35 PM
Location: Harvard Hall 104 (http://j.mp/icUlNw)

Harvard CS264 2011 Guest Lecture Series
"Massively Parallel Computing" Course
Host: Nicolas Pinto (Harvard, MIT)


The emergence of heterogeneous and many-core architectures has changed
the hardware/software interface.  While architecture innovations have
traditionally been hidden under ISA abstractions that could be
efficiently mapped to hardware, new CPU/GPU processors expose multiple
cores with heterogeneous micro-architectures directly to programmers
and languages.

Bulk-synchronous and data-parallel execution model abstractions have
risen in response.  They enable the same program representation to be
efficiently mapped to processors composed of CPU and GPU cores.  This
talk focuses on these abstractions, which have the potential to
continue the exponential increase in computing potential made possible
by technology scaling via translation to CPU, GPU, and future core
architectures that have yet to be designed.

These abstractions and the translation processes that map them to
hardware are discussed in the context of Ocelot, an open-source
dynamic compiler targeting multi-core CPUs, NVIDIA GPUs, and AMD GPUs

Speaker biography:

Gregory Diamos is a PhD candidate in the Computer Architecture and
Systems Lab at the Georgia Institute of Technology, under the
direction of Professor Sudhakar Yalamanchili, as well as a Research
Scientist at NVIDIA. He received his B.S. and M.S. in Electrical
Engineering from the Georgia Institute of Technology in 2006 and 2008,
respectively, where he focused on architecture techniques for
controlling PVT variations and runtime scheduling techniques for
heterogeneous processors.
His current research interests follow the industry shift to
heterogeneous many core architectures, where mounting communication
requirements place increasing demands on processor memory systems and
the ability to tightly integrate heterogeneous cores on-chip offers
the potential for dramatic improvements in efficiency at the cost of
increased design complexity; his research is directed toward
developing abstractions that maintain this efficiency while reducing
design complexity.

Nicolas Pinto, PhD

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